The present invention relates generally to semiconductor design technology, and more particularly, to a system and method for enabling logic circuits to adapt to different operating voltages.
Speed and peak current have always been important characteristics in integrated circuit, or "chip," designs. Speed is obviously an important characteristic because of the popular demand for faster electronic systems, such as faster computers. Peak current reduction is another important design characteristic for large-scale integrated circuits because large peak currents have a detrimental effect on the chip voltage. For example, high peak currents, combined with parasitic resistance of the chip package and wire lines, cause noise and supply voltage bounce. Furthermore, high peak currents interfere with the reliability of electron migration, potentially resulting in damage to wires inside the chip. This in turn results in the timings of individual circuits being changed, and internal timing constraints being missed, causing data to be corrupted. Furthermore, the threshold voltages of input buffers, differential amplifiers, and reference voltage generators are adversely affected by uncontrolled peak currents.
Conventional chip designs can be optimized for either peak current reduction or high speed, but not both. Therefore, chip designers have been forced to choose to optimize one over the other. This problem is exacerbated by the fact that modern integrated circuits utilize an external power supply ("V.sub.DD ") that may be set to different voltage levels. For example, one chip may require an external power supply of 3.3V, while a second chip that performs the same function may require an external power supply of 2.5V.
Conventional chips, especially those that have tight restrictions on speed and peak current, cannot always operate at different external power supplies. For example, a chip designed to operate at 3.3V would need relatively small transistors to maintain a low peak current. The 3.3V chip design, however, would be capable of meeting any speed requirements because of the higher external voltage. Conversely, a chip designed to operate at 2.5V would need relatively large transistors to facilitate high speed operation. The 2.5V chip design, however, would be capable of meeting the peak current restrictions of the chip design because of the lower external voltage.
To demonstrate the different transistor characteristics, reference is made to FIG. 1, which shows two conventional inverters 1a and 1b. The inverter 1a comprises an n-channel metal oxide semiconductor ("NMOS") transistor 2a of a first size 3a, a p-channel metal oxide semiconductor ("PMOS") transistor 4a and an output terminal 6a. The inverter 1b comprises an NMOS transistor 2b of a second size 3b, a PMOS transistor 4b and an output terminal 5b, wherein the size 3b of the transistor 2b is larger than the size 3a of the transistor 2a. As a result, the inverter 1a will draw less current than inverter 1b, while inverter 1b will transition faster than inverter 1a, as demonstrated below.
Referring to FIGS. 2 and 3 the two inverters 1a and 1b are each shown operating at 3.3V and 2.5V. Waveforms 6v and 6i represent the output voltage and current, respectively, of the inverter 1a operating at 3.3V, while waveforms 7v and 7i represent the output voltage and current, respectively, of the inverter 1b operating at 3.3V. Likewise, waveforms 8v and 8i represent the output voltage and current, respectively, of the inverter 1a operating at 2.5V, while waveforms 9v and 9i represent the output voltage and current, respectively, of the inverter 1b operating at 2.5V.
Considering the 3.3V operation example, the two inverters 1a, 1b, have timing characteristics, as illustrated in FIG. 2 by the voltage-timing waveforms 6v and 7v, respectively. However, as illustrated in FIG. 3, the peak current of inverter 1b, as shown by waveform 7i, is much greater than that of inverter 1a, as shown by waveform 6i. Therefore, the design of a chip operating at 3.3V would derive more benefit from use of the inverter la because of the reduced peak current.
Considering the 2.5V operation example, the inverter 1b is faster than the inverter 1a, as illustrated in FIG. 2 by the voltage-timing waveforms 9v and 8v, respectively. However, neither of the current waveforms 9i and 8i of the two inverters 1a, 1b, respectively, reach a very high level. Therefore, the design of the chip operating at 2.5V would derive more benefit from use of the inverter 1b.
Chip designers have dealt with multiple operating voltages in different ways. In a first solution, different chip designs are produced, one for the first operating voltage and another for the second operation voltage. For example, a first chip design would include gates like the low peak current inverter 1a for 3.3V operation, while a second chip design would include gates like the high speed inverter 1b for 2.5V operation. However, having multiple chip designs result in many difficulties, such as increased mask expense, more difficult production resulting from the need to keep the designs separated, and distribution difficulties resulting from the need to maintain the appropriate quantity of chips of each design.
A second solution is to produce a chip design that meets all the characteristic requirements of both operating voltages. For example, the chip would comprise a new inverter, with a size between 3a and 3b of FIG. 1. Although this results in a single design, the chip is not optimized for either of the two operating voltages. As a result, the chip has a poor production yield and is inferior to other chips designed exclusively for a particular operating voltage.
Therefore, what is needed is a system and method for providing a single chip with logic that adjusts to the voltage applied to the chip to maximize the efficiency of the chip with respect to speed and/or peak current.